Table of Contents
VLSI Design
Volume 2011, Article ID 756561, 8 pages
Research Article

Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method

1PG (VLSI Design), Nirma University, Ahmedabad 382481, India
2Indian Institute of Space Science & Technology, Tiruvanthapuram, India

Received 29 March 2011; Revised 14 May 2011; Accepted 29 July 2011

Academic Editor: Yangdong Deng

Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • P.R. Sruthi, and M. Nirmala Devi, “A modified scheme for simultaneous reduction of test data volume and testing power,” Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 7373, pp. 198–208, 2012. View at Publisher · View at Google Scholar
  • Manjurathi, Karen Thangam Jacob, and Ganesh Kumar, “Selective compression technique using Variable-to-Fixed coding,” International Conference on Communication and Signal Processing, ICCSP 2014 - Proceedings, pp. 1016–1020, 2014. View at Publisher · View at Google Scholar
  • Usha Sandeep Mehta, and Harikrishna Parmar, “Improvement in error resilience for compressed VLSI test data using Hamming code based technique,” 2015 International Conference on VLSI Systems, Architecture, Technology and Applications, VLSI-SATA 2015, 2015. View at Publisher · View at Google Scholar
  • HariKumar, and Manjurathi, “Test Data Compression and Power Reduction Using Similarity Based Reordering Technique for Wireless Systems,” Wireless Personal Communications, vol. 90, no. 2, pp. 713–728, 2016. View at Publisher · View at Google Scholar