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VLSI Design
Volume 2011, Article ID 845957, 13 pages
http://dx.doi.org/10.1155/2011/845957
Research Article

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Department of Electric Engineering, Technion, Israel Institute of Technology, Haifa 32000, Israel

Received 23 September 2010; Accepted 28 January 2011

Academic Editor: Shiyan Hu

Copyright © 2011 Yoni Aizik and Avinoam Kolodny. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Gracieli Posser, Guilherme Flach, Gustavo Wilke, and Ricardo Reis, “Gate sizing using geometric programming,” Analog Integrated Circuits and Signal Processing, vol. 73, no. 3, pp. 831–840, 2012. View at Publisher · View at Google Scholar
  • Gracieli Posser, Guilherme Flach, Gustavo Wilke, and Ricardo Reis, “Tradeoff between delay and area in gate sizing using Geometric Programming,” 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings, 2012. View at Publisher · View at Google Scholar
  • Mohammad Mirzaei, Mahdi Mosaffa, and Siamak Mohammadi, “Variation-aware approaches with power improvement in digital circuits,” Integration, the VLSI Journal, 2014. View at Publisher · View at Google Scholar