Table of Contents
VLSI Design
Volume 2011, Article ID 948926, 7 pages
Review Article

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

1PG-VLSI Design Group, EC Department, Institute of Technology, Nirma University, Ahmedabad 382 481, India
2Space Application Centre, Indian Space Research Organization, Ahmedabad 380 015, India

Received 3 September 2010; Accepted 23 December 2010

Academic Editor: Yangdong Deng

Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.