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VLSI Design
Volume 2011, Article ID 948926, 7 pages
http://dx.doi.org/10.1155/2011/948926
Review Article

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

1PG-VLSI Design Group, EC Department, Institute of Technology, Nirma University, Ahmedabad 382 481, India
2Space Application Centre, Indian Space Research Organization, Ahmedabad 380 015, India

Received 3 September 2010; Accepted 23 December 2010

Academic Editor: Yangdong Deng

Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Usha Mehta, Kankar Dasgupta, and Niranjan Devashrayee, “Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey,” VLSI Design, vol. 2011, Article ID 948926, 7 pages, 2011. https://doi.org/10.1155/2011/948926.