Table of Contents
VLSI Design
Volume 2011, Article ID 948926, 7 pages
http://dx.doi.org/10.1155/2011/948926
Review Article

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

1PG-VLSI Design Group, EC Department, Institute of Technology, Nirma University, Ahmedabad 382 481, India
2Space Application Centre, Indian Space Research Organization, Ahmedabad 380 015, India

Received 3 September 2010; Accepted 23 December 2010

Academic Editor: Yangdong Deng

Copyright © 2011 Usha Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. C. P. Ravikumar, M. Hirech, and X. Wen, “Test strategies for low power devices,” in Proceedings of the Design, Automation and Test in Europe (DATE '08), pp. 728–733, March 2008. View at Publisher · View at Google Scholar
  2. Y. Bonhomme et al., “Test power: a big issue in large SoC designs,” in Proceedings of The 1st IEEE Workshop on Electronic Design, Test And Applications, pp. 447–449, 2002.
  3. S. Wang and S. K. Gupta, “DS-LFSR: a new BIST TPG for low heat dissipation,” in Proceedings of the 1997 IEEE International Test Conference (ITC '97), pp. 848–857, November 1997.
  4. M. B. M. Abramovici and A. Friedman, Digital Systems Testing and Testable Design, IEEE Press, Piscataway, NJ, USA, 1990.
  5. P. Parkar, “Bare die test,” in Proceedings of IEEE Multi-Chip Module Conference, pp. 24–27, 1992.
  6. I. Polian, A. Czutro, S. Kundu, and B. Becker, “Power droop testing,” in Proceedings of the 24th International Conference on Computer Design (ICCD '06), pp. 243–250, October 2006. View at Publisher · View at Google Scholar
  7. H. Fai and N. Nicolici, “Automated scan chain division for reducing shift and capture power during broadside at-speed test,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 11, pp. 2092–2097, 2008. View at Publisher · View at Google Scholar
  8. S. J. Wang, K. L. Fu, and K. S. M. Li, “Low peak power ATPG for n-detection test,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '09), pp. 1993–1996, May 2009. View at Publisher · View at Google Scholar
  9. P. Girard, “Survey of low-power testing of VLSI circuits,” IEEE Design and Test of Computers, vol. 19, no. 3, pp. 80–90, 2002. View at Publisher · View at Google Scholar · View at Scopus
  10. M. ElShoukry, C. P. Ravikumar, and M. Tehranipoor, “Partial gating optimization for power reduction during test application,” in Proceedings of the 14th Asian Test Symposium (ATS '05), pp. 242–245, ind, December 2005. View at Publisher · View at Google Scholar
  11. P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac, “Reducing power consumption during test application by test vector ordering,” in Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (ISCAS '98), pp. 296–299, June 1998.
  12. K. Paramasivam, K. Gunavathi, and P. Sathishkumar, “Algorithm for low power combinational circuit testing,” in Proceedings of IEEE Region 10 Conference (TENCON '04), pp. D336–D339, November 2004.
  13. S. Roy, I. S. Gupta, and A. Pal, “Artificial intelligence approach to test vector reordering for dynamic power reduction during VLSI testing,” in Proceedings of the IEEE Region 10 Conference (TENCON '08), pp. 1–6, November 2008. View at Publisher · View at Google Scholar
  14. S. J. Wang, Y. T. Chen, and K. S. M. Li, “Low capture power test generation for launch-off-capture transition test based on don't-care filling,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '07), pp. 3683–3686, May 2007.
  15. S. Kundu and S. Chattopadhyay, “Efficient dont care filling for power reduction during testing,” in Proceedings of IEEE International Conference on Advances in Recent Technologies In Communication and Computing, pp. 319–323, 2009.
  16. Z. Chen, “Scan chain configuration based X filling for lowpower and high quality testing,” IET Journal on Computers and Digital Techniques, vol. 4, pp. 1–13, 2009. View at Google Scholar
  17. J.-L. Yang and Q. Xu, “State-sensitive X-filling scheme for scan capture power reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, pp. 1338–1343, 2008. View at Publisher · View at Google Scholar
  18. T. KR. Maiti and S. Chattopadhyay, “Don't care filling for power minimization in VLSI circuit testing,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), pp. 2637–2640, usa, May 2008. View at Publisher · View at Google Scholar
  19. M. Abramovici et al., Digital Systems Testing and Testable Design, Jacoba, 1997.
  20. K. Gunavathi, K. Paramasivam, P. Subashini Lavanya, and M. Umamageswaran, “A novel BIST TPG for testing of VLSI circuits,” in Proceedings of the 1st International Conference on Industrial and Information Systems (ICIIS '06), pp. 109–114, August 2006. View at Publisher · View at Google Scholar
  21. F. Corno, M. Rebaudengo, M. S. Reorda, G. Squillero, and M. Violante, “Low power BIST via non-linear hybrid cellular automata,” in Proceedings of the 18th IEEE VLSI Test Symposium (VTS '00), pp. 29–34, May 2000.
  22. X. Zhang, K. Roy, and S. Bhawmik, “POWERTEST: a tool for energy conscious weighted random pattern testing,” in Proceedings of the 12th International Conference on VLSI Design, pp. 416–422, January 1999.
  23. N. Ahmed, M. H. Tehranipour, and M. Nourani, “Low power pattern generation for BIST architecture,” in Proceedings of the IEEE International Symposium on Cirquits and Systems, pp. II689–II692, May 2004.
  24. H. Kiliç and L. Öktem, “Low-power test pattern generator design for BIST via non-uniform cellular automata,” in Proceedings of the IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT '05), vol. 2005, pp. 212–215, 2005. View at Publisher · View at Google Scholar
  25. Y. Kim, M. H. Yang, Y. Lee, and S. Kang, “A new low power test pattern generator using a transition monitoring window based on BIST architecture,” in Proceedings of the 14th Asian Test Symposium (ATS '05), pp. 230–235, December 2005. View at Publisher · View at Google Scholar
  26. K. Gunavathi, K. Paramasivam, P. Subashini Lavanya, and M. Umamageswaran, “A novel BIST TPG for testing of VLSI circuits,” in Proceedings of the 1st International Conference on Industrial and Information Systems (ICIIS '06), pp. 109–114, 2006. View at Publisher · View at Google Scholar
  27. B. Zhou, Y.-Z. Ye, Z.-L. Li, X.-C. Wu, and R. Ke, “A new low power test pattern generator using a variable-length ring counter,” in Proceedings of the 10th International Symposium on Quality Electronic Design (ISQED '09), pp. 248–252, 2009. View at Publisher · View at Google Scholar
  28. S. Wang, “A BIST TPG for low power dissipation and high fault coverage,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 7, pp. 777–789, 2007. View at Publisher · View at Google Scholar · View at Scopus
  29. M. Nourani, M. Tehranipoor, and N. Ahmed, “Low-transition test pattern generation for BIST-based applications,” IEEE Transactions on Computers, vol. 57, no. 3, pp. 303–315, 2008. View at Publisher · View at Google Scholar
  30. C. Bei, L. Xiao, and Y. Wang, “A low power deterministic test pattern generator for BIST based on cellular automata,” in Proceedings of the 4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA '08), pp. 266–269, January 2008. View at Publisher · View at Google Scholar
  31. L.-G. Hou, X.-H. Peng, and W.-C. Wu, “A low power dynamic pseudo random bit generator for test pattern generation,” in Proceedings of the International Conference on Solid-State and Integrated Circuits Technology Proceedings (ICSICT '08), pp. 2079–2082, 2008. View at Publisher · View at Google Scholar
  32. P. Girard, L. Guiller, C. Landrault et al., “Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '99), June 1999.
  33. B. Bhargab et al., “Low energy BIST design for scan-based logic circuits,” in Proceedings of 16th International Conference On VLSI Design(VLSID '03), pp. 546–551, 2003.
  34. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Test vector inhibiting technique for low energy BIST design,” in Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), pp. 407–412, April 1999.
  35. S Manich et al., “Low power BIST by filtering non detecting vectors,” in Proceedings of the IEEE European Test Workshop, pp. 317–319.
  36. Gerstendoerfer and Wunderlich, “Minimized power consumption for scan-based BIST,” in Proceedings of the IEEE International Test Conference (ITC '99), pp. 77–84, 1999.
  37. S. Hatami, M. Alisafaee, E. Atoofian, Z. Navabi, and A. Afzali-Kusha, “A low-power scan-path architecture,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '05), pp. 5278–5281, May 2005. View at Publisher · View at Google Scholar
  38. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Circuit partitioning for low power BIST design with minimized peak power consumption,” Proceedings of the Asian Test Symposium, pp. 317–319, 1999. View at Google Scholar
  39. S. Bhunia, “Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning,” in Proceedings of the 6th International Symposium On Quality of Electronic Design, pp. 453–458, 2005.
  40. Q. Xu, D. Hu, and D. Xiang, “Pattern-directed circuit virtual partitioning for test power reduction,” in Proceedings of the IEEE International Test Conference (ITC '07), pp. 1–10, October 2007. View at Publisher · View at Google Scholar
  41. S.-K. Lu, Y.-C. Hsiao, C.-H. Liu, and C.-L. Yang, “Low-power built-in self-test techniques for embedded SRAMs,” VLSI Design, vol. 2007, no. 2, pp. 1–7, 2007. View at Publisher · View at Google Scholar
  42. Y. Wu and A. Ivanov, “Low power SoC memory BIST,” in Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 197–205, October 2006. View at Publisher · View at Google Scholar
  43. YP. Xiaoming and M. Abramovici, “Sequential circuit ATPG using combination alalgorithms,” IEEE Transactions On Computer Aided Design of Integrated Circuits and Systems, vol. 24, pp. 1294–1310, 2005. View at Google Scholar
  44. G. Tavazza and E. Cervi, “Jump scan: a DFT technique for low power testing,” in Proceedings of 23rd IEEE VLSI Test Symposium, pp. 277–282, 2005.
  45. H. J. Wunderlich, “BIST for systems-on-a-chip,” Integration: The VLSI Journal, vol. 26, no. 1-2, pp. 55–78, 1998. View at Google Scholar · View at Scopus