Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2012, Article ID 173079, 18 pages
http://dx.doi.org/10.1155/2012/173079
Research Article

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

1Department of Electronics Engineering, Institute of Engineering & Technology (IET), Lucknow 226021, India
2Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology (MNNIT), Allahabad 211004, India

Received 28 June 2011; Revised 2 November 2011; Accepted 24 November 2011

Academic Editor: Jose Carlos Monteiro

Copyright © 2012 Subodh Wairya et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [15 citations]

The following is the list of published articles that have cited the current article.

  • Manoj Kumar, and R. K. Baghel, “Ultra low-power high-speed single-bit hybrid full adder circuit,” 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1–6, . View at PublisherView at Google Scholar
  • Qi Zeng, and Jih-Kwon Peir, “Content-Aware Non-Volatile Cache Replacement,” 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 92–101, . View at PublisherView at Google Scholar
  • Paro Bajpai, Priyanka Mittal, Amita Rana, and Bhupesh Aneja, “Performance analysis of a low power high speed full adder,” 2017 2nd International Conference on Telecommunication and Networks (TEL-NET), pp. 1–5, . View at PublisherView at Google Scholar
  • Vivek Saraswat, Ankur Kumar, Pratosh Kumar Pal, and R. K. Nagaria, “A survey on different modules of low-power high-speed hybrid full adder circuits,” 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON), pp. 323–328, . View at PublisherView at Google Scholar
  • A. K. Pandey, R. A. Mishra, and R. K. Nagaria, “Leakage Power Analysis of Domino XOR Gate,” ISRN Electronics, vol. 2013, pp. 1–7, 2013. View at PublisherView at Google Scholar
  • Shima Mehrabi, Reza Faghih Mirzaee, Keivan Navi, and Omid Hashemipour, “A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell,” ISRN Electronics, vol. 2013, pp. 1–8, 2013. View at PublisherView at Google Scholar
  • A. K. Pandey, R. A. Mishra, and R. K. Nagaria, “Static Switching Dynamic Buffer Circuit,” Journal of Engineering, vol. 2013, pp. 1–11, 2013. View at PublisherView at Google Scholar
  • Shipra Upadhyay, R. A. Mishra, R. K. Nagaria, and S. P. Singh, “DFAL: Diode-Free Adiabatic Logic Circuits,” ISRN Electronics, vol. 2013, pp. 1–12, 2013. View at PublisherView at Google Scholar
  • Shipra Upadhyay, R. K. Nagaria, and R. A. Mishra, “Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic,” VLSI Design, vol. 2013, pp. 1–9, 2013. View at PublisherView at Google Scholar
  • Shipra Upadhyay, Mishra, Nagaria, Singh, and Amit Shukla, “Triangular power supply based adiabatic logic family,” World Applied Sciences Journal, vol. 24, no. 4, pp. 444–450, 2013. View at PublisherView at Google Scholar
  • Saurabh Khandelwal, Neha Yadav, and Shyam Akashe, “Design and analysis of FINFET pass transistor based XOR and XNOR circuits at 45 nm technology,” 2013 International Conference on Control, Computing, Communication and Materials, ICCCCM 2013, 2013. View at PublisherView at Google Scholar
  • Mohan Shoba, and Rangaswamy Nakkeeran, “GDI based full adders for energy efficient arithmetic applications,” Engineering Science and Technology, an International Journal, 2015. View at PublisherView at Google Scholar
  • Neeraj Kumar Misra, Subodh Wairya, V. K. Singh, Neeraj Kumar Misra, Subodh Wairya, and V. K. Singh, “Optimized Approach for Reversible Code Converters Using Quantum Dot Cellular Automata,” Proceedings Of The 4Th International Conference On Frontiers In Intelligent Computing: Theory And Applications (Ficta) 2015, vol. 404, pp. 367–378, 2016. View at PublisherView at Google Scholar
  • Trapti Sharma, and Laxmi Kumre, “A Novel Energy-Efficient Hybrid Full Adder Circuit,” Advances in Data and Information Sciences, vol. 38, pp. 105–114, 2018. View at PublisherView at Google Scholar
  • Amit Kumar Pandey, Tarun Kumar Gupta, and Pawan Kumar Verma, “Sleep signal controlled footless domino circuit for low leakage current,” Circuit World, 2018. View at PublisherView at Google Scholar