VLSI Design

VLSI Design / 2012 / Article / Fig 23

Research Article

Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Figure 23

(a) Delay (ps) of XOR-XNOR-based adders. (b) Power ( W) XOR-XNOR-based adders.
173079.fig.0023a
(a)
173079.fig.0023b
(b)

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