Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
Figure 25
(a) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (2 fF) at 1.8 V. (b) PDP and EDP of XOR-XNOR based full adder cells with load capacitance (500 fF) at 1.8 V.