Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design

Table 4

Simulation results of NAND, NOR, and majority Not logic gates at 1 V.

Design	Static Majority function			MOSCAP Majority function
	Delay (ps)	Power (𝜇w)	PDP (10^−18 j)	Delay (ps)	Power (𝜇w)	PDP (10^−18 j)
NAND	36	0.041	1.47	23	0.038	0.87
NOR	40	0.042	1.68	27	0.039	1.05
Maj. Not	43	0.048	2.06	18	0.038	0.68