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VLSI Design
/
2012
/
Article
/
Tab 8
/
Research Article
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
Table 8
Area comparisons of the Majority-function-based full adder cells.
Designs
MajFA1
MajFA3
MajFA4
PMajFA1
PMajFA2
Area (
μ
m
2
)
104.5
96
97
128
64