Table of Contents
VLSI Design
Volume 2012, Article ID 268402, 15 pages
Research Article

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Department of ECE, Amrita Vishwa Vidyapeetham, Coimbatore 641 112, India

Received 26 December 2011; Revised 9 April 2012; Accepted 23 April 2012

Academic Editor: Sungjoo Yoo

Copyright © 2012 B. Bala Tripura Sundari. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Bala Tripura Sundari, and Padmanabhan, “A direct method for optimal VLSI realization of deeply nested n-D loop problems,” Microprocessors and Microsystems, vol. 37, no. 6-7, pp. 610–628, 2013. View at Publisher ยท View at Google Scholar
  • B. Bala Tripura Sundari, and Resmi, “Allocation of optimal reconfigurable array using graph merging technique,” International Conference on Embedded Systems, ICES 2014, pp. 49–54, 2014. View at Publisher ยท View at Google Scholar
  • C. Bagavathi, and O. Saraniya, “Evolutionary Mapping Techniques for Systolic Computing System,” Deep Learning and Parallel Computing Environment for Bioengineering Systems, pp. 207–223, 2019. View at Publisher ยท View at Google Scholar