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VLSI Design
Volume 2012, Article ID 273276, 12 pages
http://dx.doi.org/10.1155/2012/273276
Research Article

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

1Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham University, Coimbatore 641112, India
2Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore 641004, India

Received 3 February 2012; Revised 19 August 2012; Accepted 23 September 2012

Academic Editor: Dinesh Mehta

Copyright © 2012 D. S. Harish Ram et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [19 citations]

The following is the list of published articles that have cited the current article.

  • Anirban Sengupta, and Vipul Kumar Mishra, “Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment,” 2014 International Conference on Information Technology, pp. 281–286, . View at Publisher · View at Google Scholar
  • Vipul Kumar Mishra, and Anirban Sengupta, “Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis,” 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 66–68, . View at Publisher · View at Google Scholar
  • Vipul Kumar Mishra, and Anirban Sengupta, “PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis,” 2014 Fifth International Symposium on Electronic System Design, pp. 10–14, . View at Publisher · View at Google Scholar
  • Anirban Sengupta, and Vipul Kumar Mishra, “Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis,” Fifteenth International Symposium on Quality Electronic Design, pp. 60–67, . View at Publisher · View at Google Scholar
  • D. S. H. Ram, M. C. Bhuvaneswari, and S. Umadevi, “Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II -based Schedule Selection,” Advances in Electrical and Computer Engineering, vol. 13, no. 4, pp. 85–92, 2013. View at Publisher · View at Google Scholar
  • Anirban Sengupta, and Vipul Kumar Mishra, “Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm,” Expert Systems With Applications, vol. 41, no. 10, pp. 4691–4703, 2014. View at Publisher · View at Google Scholar
  • Anirban Sengupta, and Saumya Bhadauria, “Exploration of multi-objective tradeoff during high level synthesis using bacterial chemotaxis and dispersal,” Procedia Computer Science, vol. 35, no. C, pp. 63–72, 2014. View at Publisher · View at Google Scholar
  • Vipul Kumar Mishra, and Anirban Sengupta, “MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design,” Advances in Engineering Software, vol. 67, pp. 111–124, 2014. View at Publisher · View at Google Scholar
  • Vipul Kumar Mishra, and Anirban Sengupta, “Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligence,” International Journal of Knowledge-Based and Intelligent Engineering Systems, vol. 19, no. 1, pp. 47–61, 2015. View at Publisher · View at Google Scholar
  • V.K. Mishra, and A. Sengupta, “Swarm-inspired exploration of architecture and unrolling factors for nested-loop-based application in architectural synthesis,” Electronics Letters, vol. 51, no. 2, pp. 157–159, 2015. View at Publisher · View at Google Scholar
  • Bhuvaneswari, D. S. Harish Ram, and Neelavenipp. 69–92, 2015. View at Publisher · View at Google Scholar
  • Anirban Senguptapp. 113–124, 2015. View at Publisher · View at Google Scholar
  • Anirban Sengupta, and Saraju P. Mohantypp. 219–266, 2016. View at Publisher · View at Google Scholar
  • Anirban Sengupta, and Saumya Bhadauria, “Exploring Low Cost Optimal Watermark for Reusable IP Cores during High Level Synthesis,” IEEE Access, vol. 4, pp. 2198–2215, 2016. View at Publisher · View at Google Scholar
  • Anirban Sengupta, Saumya Bhadauria, and Saraju P. Mohanty, “TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling with Optimal Loop Unrolling Factor during High Level Synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 4, pp. 660–673, 2017. View at Publisher · View at Google Scholar
  • Anirban Sengupta, Saumya Bhadauria, and Saraju P. Mohanty, “Low-cost security aware HLS methodology,” IET Computers and Digital Techniques, vol. 11, no. 2, pp. 68–79, 2017. View at Publisher · View at Google Scholar
  • Pallabi Sarkar, Anirban Sengupta, Santosh Rathlavat, and Mrinal Kanti Naskar, “Designing Low-Cost Hardware Accelerators for CE Devices [Hardware Matters],” IEEE Consumer Electronics Magazine, vol. 6, no. 4, pp. 140–149, 2017. View at Publisher · View at Google Scholar
  • Darian Reyes Fernández De Bulnes, and Yazmin Maldonado, “VHDL code generation as State Machine from a Data Flow Graph,” 2016 IEEE International Autumn Meeting on Power, Electronics and Computing, ROPEC 2016, 2017. View at Publisher · View at Google Scholar
  • Darian Reyes Fernández De Bulnes, Juan Carlos Dibene Simental, Yazmin Maldonado, and Leonardo Trujillo, “High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices,” AI Communications, vol. 30, no. 2, pp. 151–168, 2017. View at Publisher · View at Google Scholar