VLSI Design / 2012 / Article / Tab 6 / Research Article
A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths Table 6 Comparison of WSGA and WSPSO on DFG benchmarks.
Benchmark WSGA WSPSO
Reduction in execution times% Power Area (register units) Delay (time steps) Execution time (seconds) Power Area (register units) Delay (time steps) Execution time (seconds) IIR 0.9019 48.48 5.148 6 0.9083 35.93 5.86 4 33.33% HAL 0.9901 37.81 4.981 11 0.9960 33.75 4.98 8 27.27% DWT 0.7126 50.92 10 26 0.7242 26.57 10.11 14 46.15% FIR 0.6416 54.48 11.32 112 0.6595 44.68 10.59 97 13.39% MPEG motion vector 0.6714 107.5 9 48 0.6984 95.30 7.69 34 29.17% DCT 0.6086 79.06 12.18 1528 0.6120 75.98 11.30 1408 7.85%