A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Table 3

Wirelengths and insertion times.

Design	No. of SC	Wirelength		Slack (%)	Insertion time (ms)
		GL-S	RTL-S		𝑃-graph	TSP
ITC 99 Benchmarks (VHDL)
b09	2	2.06	1.63	−20.59	<1	<1
b10	2	1.94	2.06	5.97	10	<1
b11	3	4.77	5.03	5.38	20	10
b12	10	12.6	12.92	2.59	200	20
b13	5	3.39	3.32	−2.25	20	<1
b14	24	63.64	64.2	0.96	3 s	110
b15	24	126.3	122	−3.39	6 s	320
b17	70	395.6	370.4	−6.37	30 s	3 s
b18	300	1187.2	922.6	−22.29	3 m	10 s
b19	600	2329.6	1858.2	−20.24	5 m	20 s
Opencore designs (Verilog)
Simple-Spi	10	11.5	10.4	−8.95	100	20
Biquad	20	34.1	31.3	−8.14	350	80
Ac-97	200	247.7	238.5	−3.71	30 s	8 s