Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

<table>Content of a typical SHAPES tile [<a href="/journals/vlsi/2012/450302/#B53">45</a>].</table>

VLSI Design

fig3

Figure 3

Figure 3: Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing 

Figure 3 | Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing 