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VLSI Design
Volume 2012, Article ID 575389, 13 pages
Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

1Department of Electronics and Communication Engineering, Vel Tech Dr. RR and Dr. SR Technical University, Avadi, Tamil Nadu, Chennai 600 062, India
2Department of Electronics and Communication Engineering, S.A. Engineering College, Anna University, Thiruverkadu, Tamil Nadu, Chennai 600 077, India
3School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK

Received 8 October 2011; Revised 24 January 2012; Accepted 17 March 2012

Academic Editor: Sungjoo Yoo

Copyright © 2012 P. Balasubramanian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • P. Balasubramanian, and R. T. Naayagi, “Redundant logic insertion and fault tolerance improvement in combinational circuits,” 2017 International Conference on Circuits, System and Simulation (ICCSS), pp. 6–13, . View at Publisher · View at Google Scholar
  • P. Balasubramanian, C. Dang, D.L. Maskell, and K. Prasad, “Asynchronous early output section-carry based carry lookahead adder with alias carry logic,” 2017 IEEE 30th International Conference on Microelectronics (MIEL), pp. 293–298, . View at Publisher · View at Google Scholar
  • P. Balasubramanian, and S. Yamashita, “Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders,” Springerplus, vol. 5, 2016. View at Publisher · View at Google Scholar
  • Padmanabhan Balasubramanian, Douglas Maskell, and Nikos Mastorakis, “Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic,” Electronics, vol. 7, no. 10, pp. 243, 2018. View at Publisher · View at Google Scholar