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VLSI Design
Volume 2012 (2012), Article ID 575389, 13 pages
http://dx.doi.org/10.1155/2012/575389
Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

1Department of Electronics and Communication Engineering, Vel Tech Dr. RR and Dr. SR Technical University, Avadi, Tamil Nadu, Chennai 600 062, India
2Department of Electronics and Communication Engineering, S.A. Engineering College, Anna University, Thiruverkadu, Tamil Nadu, Chennai 600 077, India
3School of Computer Science, The University of Manchester, Oxford Road, Manchester M13 9PL, UK

Received 8 October 2011; Revised 24 January 2012; Accepted 17 March 2012

Academic Editor: Sungjoo Yoo

Copyright © 2012 P. Balasubramanian et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

P. Balasubramanian, D. A. Edwards, and W. B. Toms, “Redundant Logic Insertion and Latency Reduction in Self-Timed Adders,” VLSI Design, vol. 2012, Article ID 575389, 13 pages, 2012. doi:10.1155/2012/575389