VLSI Design

VLSI Design / 2012 / Article / Fig 13

Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Figure 13

(a) Self-timed system handling heterogeneously encoded inputs and outputs, (b) dual-rail to 1-of-4 encoder, (c) 1-of-4 to dual-rail decoder.
575389.fig.0013a
(a)
575389.fig.0013b
(b)
575389.fig.0013c
(c)

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