VLSI Design

VLSI Design / 2012 / Article / Fig 2

Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Figure 2

Timing diagram of a 4-phase handshake discipline.
575389.fig.002

Article of the Year Award: Outstanding research contributions of 2020, as selected by our Chief Editors. Read the winning articles.