VLSI Design

VLSI Design / 2012 / Article / Fig 5

Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Figure 5

n-bit dual-rail encoded self-timed carry-ripple adder structure.
575389.fig.005

Article of the Year Award: Outstanding research contributions of 2020, as selected by our Chief Editors. Read the winning articles.