Journals
Publish with us
Publishing partnerships
About us
Blog
VLSI Design
Table of Contents
Special Issues
VLSI Design
/
2012
/
Article
/
Fig 9
/
Research Article
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
Figure 9
Dual-rail encoded
n
-bit RCA architecture comprising dual-bit adder blocks.