VLSI Design

VLSI Design / 2012 / Article / Tab 1

Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Table 1

Data representation via dual-rail and 1-of-4 encoding formats.

Single-rail inputsDual-rail encoded data1-of-4 encoded data
( )( ) E3

00(0 1)(0 1)0001
01(0 1)(1 0)0010
10(1 0)(0 1)0100
11(1 0)(1 0)1000

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