VLSI Design

VLSI Design / 2012 / Article / Tab 2

Research Article

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

Table 2

Delay, area, and power of various nonredundant 32-bit self-timed RCAs.

Adder realization styleDelay (ns)Area (μm2)Power (μW)

SSSC_HIE_NRL (weak)8.06633 (78)619.1
DIMS_DSSC_DRE (weak)* [25]12.821833 (1202)1025.9
Toms_DSSC_DRE (strong) [33]9.410793 (512)693.1
Toms_DSSC_HE (strong) [33]9.012121 (479)695.9
Folco et al._DSSC_DRE (weak) [34]5.99417 (426)740.4
DSSC_DRE (weak)5.914921 (770)871.9
DSSC_HE (weak)5.810889 (402)688.4

The dual sum, single carry (DSSC) adder realization based on the DIMS method required careful speed-independent logic decomposition to decompose the high fan-in C-gates.

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