Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Algorithm 1

Worst case configuration identification.

Input: A set of 𝐾 candidate ASIP configurations

Output: Worst Case Configuration (WCC)

𝑁_IS(WCC)=1;

RF_size(1,WCC)=0;

FU_set(1,WCC)={};

for  each candidate configuration 𝑐 with 𝑐=1,…,𝐾  do

 𝑁_IS(WCC)=max{𝑁_IS(𝑖)};            with 𝑖=1,…,𝑐

 for each issue slot 𝑥 of the configuration 𝑐  do

   RF_size(𝑥,WCC)=max{RF_size(𝑥,𝑖)};        with 𝑖=1,…,𝑐

   FU_set(𝑥,WCC)=FU_set(𝑥,𝑐)∪FU_set(𝑥,𝑖);   with 𝑖=1,…,𝑐

 end

end