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VLSI Design
Volume 2012, Article ID 580584, 16 pages
http://dx.doi.org/10.1155/2012/580584
Research Article

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

1Department of Electrical and Electronic Engineering, University of Cagliari, 09123 Cagliari, Italy
2Silicon Hive B.V., High Tech Campus, 5656AE Eindhoven, The Netherlands

Received 15 September 2011; Revised 22 December 2011; Accepted 22 December 2011

Academic Editor: Lech Jozwiak

Copyright © 2012 Paolo Meloni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer, “Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper,” VLSI Design, vol. 2012, Article ID 580584, 16 pages, 2012. https://doi.org/10.1155/2012/580584.