Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper

Table 1

Area models dependency recap. Subscripts for operations separate operation count for the single issue slot (IS) from the overall processor count (𝑃).

	Area
FU	∝ FU_Port_Size
IS mux logic	∝#operationsIS
Register File	∝ RF depth, RF width
Decoder	∝#operations𝑃
Result select network	∝#operations𝑃(#RF ports + #IS output_ports)
Sequencer	constant
FIFOs	∝ Mem_size
Program memory	∝ Mem_size
Data memory	∝ Mem_size