Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

<table>Disparity maps of the Tsukuba and Venus image pairs for the system configurations listed in Table <a href="../tab3/">3</a>. From left to right: ground truth disparity map and disparity maps generated by System 1, System 2, System 3, and System 4, respectively.</table>

VLSI Design

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Figure 10

Figure 10: Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms 