Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Table 7

Comparison of PDS performance for various systems and methods.

Work	Image size	Disparity Range	Frame rate (fps)	PDS (10^6)	Algorithm	Platform
Yang and Pollefeys [12]	512 × 512	32	N/A	289	Block-matching (SAD)	ATI Radeon 9800 graphics card
Yang et al. [13]	384 × 288	16	12.77	22.2	Hierarchical belief propagation	NVIDIA Geforce 7900 GTX graphics card
Khaleghi et al. [15]	160 × 120	30	20	11.5	Census transform based	BlackFin processor-ADSP-BF561 (600 MHz)
Zinner and Humenberger [16]	450 × 375	60	11.8	119.5	Census transform based	Texas Instruments TMS320C6414 DSP
Hile and Zheng [19]	512 × 480	32	30	235.9	Block-matching (SAD)	N/A
Miyajima and Maruyama [20]	640 × 480	80	26	639	Block-matching (SAD)	ADM-XRC-II (40 MHz)
Arias-Estrada and Xicotencatl [22]	320 × 240	16	71	87.2	Block-matching (SAD)	XCV800HQ240-6 (66 MHz)
Lee et al. [23]	640 × 480	64	30	589	Block-matching (SAD)	XC2V8000 (10 MHz)
Hariyama et al. [24]	64 × 64	64	5063	1327.2	Block-matching (SAD)	APEX20KE (86 MHz)
Georgoulas and Andreadis [25]	800 × 600	80	550	21120	Block-matching (SAD)	EP4SGX290 (511 MHz)
Ambrosch et al. [26]	450 × 375	100	600	10125	Block-matching (SAD)	EP2S130 (110 MHz)
Díaz et al. [27]	1280 × 960	29	52	1885	Phase based	Custom FPGA, Xilinx Virtex-II (65 MHz)
Darabiha et al. [28]	256 × 360	20	30.3	55.2	LWPC (phase correlation)	TM-3A board (Xilinx Virtex-4 2000E FPGA)
Jin et al. [29]	640 × 480	64	230	4522	Census transform	Virtex-5 XC4VLX200-10 FPGA (93.1 MHz)
Chang et al. [30]	352 × 288	64	42	272.5	Minicensus adaptive support weight	UMC 90ns Std. Cell
Ambrosch and Kubinger [31]	750 × 400	60	60	1080	SAD-IGMCT	Altera Stratix I (133 MHz)
Proposed (System 2)	1280 × 1024	120	150	23592	Edge-based fixed support weight block matching (SAD)	ML505 Evaluation Board with Virtex-5 LX110T FPGA (100 MHz)
Proposed (System 4)	800 × 600	64	30	922	Edge-based adaptive support weight block matching (SAD)	ML505 Evaluation Board with Virtex-5 LX110T FPGA (155 MHz)