VLSI Design

VLSI Design / 2012 / Article / Tab 2

Research Article

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 2

Truth table for (a) two input AND gate and (b) two input OR gate.
(a)

ANDS0S1T0T1P0P1X

S0S0S0S0S0S0S0S0
S1S0S1T0T1P0P1X
T0S0T0T0P0P0T0X
T1S0T1P0T1P0T1X
P0S0P0P0P0P0P0X
P1S0P1T0T1P0P1X
XS0XXXXXX

(b)

ORS0S1T0T1P0P1X

S0S0S1T0T1P0P1X
S1S1S1S1S1S1S1S1
T0T0S1T0P1T0P1X
T1T1S1P1T1T1P1X
P0P0S1T0T1P0P1X
P1P1S1P1P1P1P1X
XXS1XXXXX

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