VLSI Design

VLSI Design / 2012 / Article / Tab 3

Research Article

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 3

The ISCAS’85 and scan version of ISCAS’89 circuit characteristics.

CircuitNumber of inputsNumber of outputsNumber of GatesNumber of pathsNumber of critical pathsNumber of victimsTotal target faults

c17526116742
c4323671608392621991039327
c8806026383864292709279
c499413220294401420721879
c19083325880729057329325916
s2774102861074
s208191096145218743
s208.1189104142112558
s2981720119231110537
s5262427193410110891
s386131315920710494195
s51025132113691131098
s420.134172184741141276
s11963232529309795510630
s12383232508355830455822
s13207.170079079511345319565188241743
s15850.161168497721647380358238341240814

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