VLSI Design

VLSI Design / 2012 / Article / Tab 6

Research Article

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 6

Comparison with previous works.

Circuit namePrevious work [6]Previous work [12]Previous work [13]Proposed ATPG
% Fault coverageTime(s)% Fault coverageTime(s)% Fault coverageTime(s)% Fault coverageTime(s)

c432351019154 hr 42 min80338.05
c880281553382 hr 27 min54.260.1801268.5
c1355163173363 hr 48 min331865.8
c1908332562810 hr 40 min24.34360153762.3
c5315317030124 hr 10 min497.85577151.2
c7552148424228 hr 26 min521326.6689867.03

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