VLSI Design

VLSI Design / 2012 / Article / Tab 7

Research Article

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Table 7

Comparison with previous works.

Circuit namePrevious work [8]Previous work [9]Previous work [18]Proposed ATPG
% Fault coverageTime(s)% Fault coverageTime(s)% Fault coverageTime(s)% Fault coverageTime(s)

s20831.500.1855.480.2691.233
s29842.660.17843.317
s38634.430.5551.890.36215.26
s52666.300.1955.240.28612.033
s420.127.190.50229.3
s119631.320.671.030.48.4119621404
s12383.830.23.111687704.5
s13207.187.141432925.13182876432333.5
s15850.183.05196273.15833715397136.4

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