Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder

Table 5

Synthesis results for the intraframe mode decision architecture.

FPGA Altera Stratix II			TSMC 0.18 μm standard cells
Number of ALUTs	Number of DLRs	Frequency (MHz)	Area (Number of gates)	Frequency (MHz)
3,267	2,312	98.43	28,518	129.10