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VLSI Design
Volume 2012 (2012), Article ID 948957, 7 pages
Research Article

Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

1ASIC and System Department, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China
2DSP Software Department, Datang Mobile Communications Equipment Co., Ltd., Beijing 100083, China

Received 27 June 2011; Revised 15 December 2011; Accepted 30 December 2011

Academic Editor: Sungjoo Yoo

Copyright © 2012 Zhen-dong Zhang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm2, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.