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Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design
We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design.
For many manufacturers and product developers, it is a good idea to reduce power consumption in electronic products. It is also an important idea to gain competitive advantage in an increasingly power hungry world. Low power consumption gives many benefits to designers and to users; for example, the main advantage is that it reduces stringent cooling requirements and it results in inexpensive and more compact products . The rapid rise in power requirements has promoted governments and industry to increase energy efficiency and design low power components. The majority of frequency synthesis techniques fall into two categories: either direct frequency synthesis or indirect frequency synthesis . To achieve fine frequency steps, the direct frequency synthesis technique is used because it is based on using digital techniques. To generate multiples (integer or noninteger) of a reference frequency, indirect frequency synthesis is used because it is based on a phase-locked loop (PLL). Here, the latter technique is used because we are going to implement PLL. It is used to generate a signal whose phase is related to the phase of the input signal and this signal is called an output signal of the PLL. The input signal is called the “reference” signal. In a feedback loop, the oscillator is controlled by the output signal from the phase detector [3, 4]. The circuit compares the phase of a signal obtained from its output oscillator with the phase of the input signal to keep the phases matched by adjusting the frequency of its oscillator. A phase locked loop (PLL) architecture has two types, a Fractional-N PLL (FNPLL) and an integer-N PLL . For a given frequency resolution, the latter has high reference frequency than the former, and, hence, the loop bandwidth which is limited to 10% of the reference frequency can be set larger in the FNPLL than in the integer-N-PLL. Therefore, the latter architecture is used for faster locking. This speed advantage of the FNPLL, however, comes at the price of increased design complexity . This is because the fractional-N operation in steady state requires fractional spur reduction circuits whose quantization noise folds into the PLL spectrum via loop nonlinearities, demanding more significant design efforts to minimize the loop nonlinearities. On the contrary, in the absence of fractional spurs, integer-N-PLLs involve less design complexity. Here, FNPLL is required. The expression of output frequency of the FNPLL is
In this equation, is an integer, and is the fractional part. To obtain the desired fractional division ratio dual modulus is used . Using the sigma-delta modulation technique, we can remove the fractional spurs. This technique generates a random integer number. The average of these random numbers will result in the desired ratio. A phase detector, a loop filter, and a voltage controlled oscillator (VCO) are the main parts of phase-locked loop, as shown in Figure 1.
The important part of the phase-locked loop (PLL) is phase detector. It is also called a phase comparator, logic circuit, frequency mixer, or an analog multiplier that generates a voltage signal and this voltage signal shows the phase difference. Three units are coupled as a feedback system as shown in Figure 1. The periodic output signal is generated by the oscillator. The applications of PLL are versatile; for example, it can generate different stable frequencies or it can obtain a signal from noisy signals. A complete phase-locked loop block can be obtained from single integrated circuit. This technique is used in advanced electronic products which have different output frequencies from some Hz to many Giga Hz . To get low power consumption, high speed, and stability, we decide to design phase-locked loop of architecture fractional-n using 0.12 micrometer CMOS/VLSI design. As the demand of PLL is growing day by day in the field of communications, low leakage transistors will be used for maintaining low power but for this we have to make a little compromise on frequency.
The structure of FNPLL is depicted in Figure 2. We can control characteristics of PLL by using low pass filter, for example, transients response and bandwidth. The basic and essential functional unit of PLL is VCO. VCO is used for clock generation . For synthesizing aspired frequencies, we use PLL with arbitrary frequency division (+N) method. This proposed technique has the ability to give fast settling time, reduce phase noise, and also reduce the effect of spurious frequencies when compared with existing FNPLL techniques.
2. PLL Design Using 0.12 Micrometer
2.1. Phase Detector
The first block has two inputs, the reference input and the feedback. It compares frequencies of input and produces an output using phase difference of inputs. To represent this block XOR gates are used. The gate produces a square wave when one-fourth of period shift of 90 degrees takes place at clock input, whereas output is different for all other angles. We apply output of the XOR gates to LPF which results in analog voltage, proportional to phase difference.
2.2. Loop Filter
To get pure DC voltage along with rectifiers filters, the electronic circuits are also used. The second block of PLL is loop filter and it has two distinct functions. First, maintains stability, that is defined by describing the loop dynamics. This explains the response of the loop to uncertainties. The 2nd function is applied to the VCO control input which appears at the phase detector output. This frequency produces FM sidebands and modulates the VCO . Other features of the PLL, for example, bandwidth, transient response, lock range, and capture range, can be controlled by LPF. The LPF is used to attenuate this energy, but it can also reject band. The low pass filter can be obtained by using a capacitor of large value and the capacitor is charged and discharged with the help of the switch resistance . By the help of .C delay a low pass filter can be created. Figure 6 depicts a CMOS schematic of phase detector with loop filter, Figure 7 shows layout, and Figure 8 shows output waveform.
2.3. Voltage Controlled Oscillator
As VCO is a source of varying output signal so the frequency of the output signal is regulated over a DC voltage range. The output signal can be a square wave or a triangular wave form. The oscillation frequency is controlled by the value of input voltage . Figure 9 shows a CMOS circuit of VCO, Figure 10 shows layout, and Figure 11 shows output waveform.
2.4. Sigma-Delta Modulator
Sigma-delta modulation technique is used to convert high definition signals to low definition signals in digital domain. We designed sigma-delta modulator using 0.12 micrometer feature size and then the layout was obtained. The input is the aspired fractional number () and the output is the sum of quantization noise and a DC part [12, 13]. By the use of integer divider quantization noise was generated. Figures 12 and 15 show the CMOS circuit; Figures 13 and 16 show the layout of comparator and operational transconductance amplifier. Figures 14 and 17 show the output waveforms.
Power usage and heat dissipation are one of the biggest challenges of VLSI industry today. In order to design the low power consuming component, without making significant change in performance, the design of FNPLL frequency synthesizer was implemented and simulated. The optimized design was implemented to 0.12 micrometer technology. Using CMOS logic, the schematics were designed and verified functionally and then prefabrication layout was sketched. The simulation curves of the layouts reflected reduction in power consumption, for the optimized design.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
- R. Jacob Baker, CMOS Circuit Design, Layout and Simulation, IEEE Press, John Wiley & Sons, 3rd edition, 2010.
- A. Anil and R. K. Sharma, “A high efficiency charge pump for low voltage devices,” International Journal of VLSI Design & Communication Systems, vol. 3, no. 3, 2012.
- U. L. Rohde, Digital PLL Frequency Synthesis, Prentice-Hall, Englewood Cliffs, NJ, USA, 1983.
- B. K. Mishra, S. Save, and S. Patil, “Design and analysis of second and third order PLL at 450 MHz,” International Journal of VLSI Design & Communication Systems, vol. 2, no. 1, 2011.
- N. Weste and D. Harris, CMOS VLSI Design—A Circuits and Systems Perspective, Pearson Education, 3rd edition, 2005.
- U. A. Belorkar and S. A. Ladhake, “Design of low power phase lock loop using 45 nm VLSI technology,” International Journal of VLSI Design & Communication Systems, vol. 1, no. 2, 2010.
- T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, “Delta-Sigma modulation in fractional-n frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, 1993.
- M. H. Perrott, “Fractional-N Frequency Synthesizer Design Using The PLL Design Assistant and CppSim Programs,” July 2008.
- S. Franssila, Introduction to Microfabrication, John Wiley & Sons, 2004.
- K. Woo, Y. Liu, E. Nam, and D. Ham, “Fast-lock hybrid PLL combining fractional-N and integer-N modes of differing bandwidths,” IEEE Journal of Solid-State Circuits, vol. 43, no. 2, pp. 379–389, 2008.
- N. Fatahi and H. Nabovati, “Design of low noise fractional-N frequency synthesizer using sigma-delta modulation technique,” in Proceedings of the 27th International Conference on Microelectronics (MIEL '10), pp. 369–372, IEEE, May 2010.
- S. Borkar, “Obeying Moore's law beyond 0.18 micron,” in Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, pp. 26–31, September 2000.
- R. K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, “High-performance and low-power challenges for sub-70 nm microprocessor circuits,” in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 125–128, May 2002.
Copyright © 2014 Sahar Arshad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.