Table of Contents
VLSI Design
Volume 2014, Article ID 406416, 7 pages
http://dx.doi.org/10.1155/2014/406416
Research Article

Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

1Department of Electronic Engineering, University College of Engineering and Technology, The Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan
2Scholar Teacher Research Alliance for Problem Solving (STRAPS), Bahawalpur 63100, Pakistan
3Department of Computer System Engineering, University College of Engineering and Technology, The Islamia University of Bahawalpur, Bahawalpur 63100, Pakistan

Received 10 May 2014; Accepted 7 June 2014; Published 23 July 2014

Academic Editor: Yu-Cheng Fan

Copyright © 2014 Sahar Arshad et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design.