Gate-Level Circuit Reliability Analysis: A Survey

<table>The relative error of circuit reliability <svg height="15.45" id="M94" style="vertical-align:-3.24037pt" version="1.1" viewbox="0 0 20.0875 15.45" width="20.0875" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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</svg> of Figure <a href="../fig3/">3</a> versus the number of MC simulation runs <svg height="15.4375" id="M95" style="vertical-align:-3.25792pt" version="1.1" viewbox="0 0 34.012501 15.4375" width="34.012501" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
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<g transform="matrix(.012,-0,0,-.012,14.925,15.187)"><path d="M861 0h-263v28q61 5 73 22t12 97l-4 408h-4l-244 -548h-20l-224 534h-2l-15 -285q-5 -98 -3 -166q1 -34 19.5 -45t72.5 -17v-28h-233v28q45 5 62.5 17t22.5 43q11 65 19 183l14 208q3 36 3.5 55t-2.5 37.5t-6.5 25t-16.5 13t-25.5 8t-39.5 4.5v28h164l228 -501l232 501
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VLSI Design

Gate-Level Circuit Reliability Analysis: A Survey

Figure 4