Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits

Figure 8

(a) Full-adder circuit in the form of “.pla” (full adder with 3 inputs () and 2 outputs ()). (b) Chromosome encoding by assigning polarities to input variables. Input variable encoding (: negative polarity; and : positive polarity).

(a)

(b)