New Proposal for MCML Based Three-Input Logic Implementation

Table 1

Summary of the results.

Parameter	Circuit
	Conventional; MCML	Topology 1	Topology 2	Proposed	CMOS; CPL
Supply voltage ()	1.7 V	1.1 V	1.4 V	1.1 V	1.0 V
Power consumption (μW)	170	110	140	110	44
Propagation delay (ps)	1178	1049	732	614	4017
Power delay product (fJ)	166.770	115.390	102.480	67.540	176.748
Gate count	1	2	1	1	1
Transistor count	17	20	18	22	18
Switching current (μA)	5	40	25	20	42