VLSI Design

Volume 2016, Article ID 8712768, 10 pages

http://dx.doi.org/10.1155/2016/8712768

## New Proposal for MCML Based Three-Input Logic Implementation

^{1}Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India^{2}Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi, India

Received 31 December 2015; Revised 8 June 2016; Accepted 19 July 2016

Academic Editor: Spyros Tragoudas

Copyright © 2016 Neeta Pandey et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

This paper presents a new proposal for three-input logic function implementation in MOS current mode logic (MCML) style. The conventional realization of such logic employs three levels of stacked source-coupled transistor pairs. It puts restriction on minimum power supply requirement and results in increased static power. The new proposal presents a circuit element named as quad-tail cell which reduces number of stacked source-coupled transistor levels by two. A three-input exclusive-OR (XOR) gate, a vital element in digital system design, is chosen to elaborate the approach. Its behavior is analyzed and SPICE simulations using TSMC 180 nm CMOS technology parameters are included to support the theoretical concept. The performance of the proposed circuit is compared with its counterparts based on CMOS complementary pass transistor logic, conventional MCML, and cascading of existing two input tripple-tail XOR cells and applying triple-tail concept in conventional MCML topology. It is found that the proposed XOR gate performs best in terms of most of the performance parameters. The sensitivity of the proposed XOR gate towards process variation shows a variation of 1.54 between the best and worst case. As an extension, a realization of 4 : 1 multiplexer has also been included.

#### 1. Introduction

MCML style finds application in communication systems, optical fiber links, digital to analog converter, microprocessors, and signal processors [1–3]. As compared to static CMOS logic, MCML has several advantageous features such as improved signal integrity, reduced power consumption, better power delay product at high frequencies, stability with technology generations, and improved security in cryptography applications [4–9]. A MCML gate consists of three main parts, namely, a pull down network (PDN), a current source, and a load. The PDN implements the logic function; the current source generates the constant bias current while the load performs the current-to-voltage conversion.

The logic function is realized using series-gating approach which suggests stacking of the source-coupled transistors pairs in the PDN. The number of stacked levels has a direct correspondence with number of inputs in the logic function. As the number of inputs becomes larger, there is increase in the number of stacked levels (NSL). For proper operation of MCML gate, a minimum power supply is required which is decided by the value of NSL and higher NSL result in larger minimum power supply. This serves as a main motivation behind using low voltage topology as lower power supply will result in reduced power consumption since the latter is computed as the product of bias current and power supply. Few low voltage techniques are available in the open literature [10–16]. The techniques [10–13] provide single ended output. A NOR based logic realization is proposed in [10, 11] to avoid stacking but it requires multistage realization of logic function. Additional current mirror, voltage, and current source are employed in [12, 13] to avoid stacking. The triple-tail cell concept is introduced in [14–16] to reduce NSL by one for the two-level MCML gates implementation. This paper introduces a new methodology for reducing the value of NSL by two and presents a quad-tail cell for this purpose. This method therefore allows three-input logic function realization using single level of source-coupled pairs and ultimately resulting in significant reduction in minimum power supply. A total of four proposed quad-tail cells are used for three-input logic function. The outlined method is generic in nature and can be applied to realize any three-input function.

The paper first discusses the basic realization of the three-input logic function in MCML style in Section 2. XOR gate is chosen for the purpose. Thereafter, Section 3 presents the new quad-tail cell put forward and its usefulness is illustrated through MCML XOR gate realization. The operation of the proposed XOR gate is explained and analytical formulations for the minimum power supply and voltage swing are put forward. Its performance comparison with the CMOS complementary pass transistor logic (CPL) based XOR gate, traditional MCML topology, and the two additional topologies is included in Section 4. A discussion on the general approach for implementing complex logic function in MCML style is also included. Extensive SPICE simulations are carried out to validate the proposed theory. Section 5 concludes the paper.

#### 2. Conventional Three-Input MCML Gate Realization

The basic architecture of MCML gate consists of a pull down network (PDN), a current source, and a load as shown in Figure 1(a). The PDN implements the logic function, the current source maintains a constant bias current, and the load performs the current-to-voltage conversion [4]. The gate works on the principle of current steering. Depending upon the inputs, the bias current is steered to one of the output branches and produces the output accordingly. The logic function is realized by using series-gating approach [17]. It is a systematic and a general approach wherein a logic function is implemented as a network of source-coupled transistor pairs having all transistor paths associated with the possible input combinations and then properly connecting each of the upper drain nodes to the output nodes. Based on this, the schematic of MCML XOR gate with differential inputs A, B, and C is shown in Figure 1. The PDN has three levels of source-coupled transistor pairs (2–15), the load transistors (16, 17), and a constant current source 1 that generates the bias current . The differential inputs A, B, and C drive the uppermost (8–15), middle (4–7), and lowest (2-3) levels, respectively. Consider, for instance, that all the inputs are high. Under this condition, the bias current is steered in transistors 2, 4, and 9 such that high and low voltages are obtained at the nodes and through the load transistors.