Table of Contents
VLSI Design
Volume 2017, Article ID 1030249, 9 pages
Research Article

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

1College of Information Engineering, Capital Normal University, Beijing 100048, China
2Department of Electrical and Computer Engineering, University of Delaware, Newark, DE, USA
3Beijing Advanced Innovation Center for Imaging Technology, Beijing, China

Correspondence should be addressed to Keni Qiu; nc.ude.unc@nkuiq

Received 6 June 2017; Accepted 22 October 2017; Published 22 November 2017

Academic Editor: Chien-In Henry Chen

Copyright © 2017 Yuanhui Ni et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.