Research Article
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers
Table 1
Parameters of SRAM, SLC STT-RAM, and MLC STT-RAM.
| | Parameters | SRAM | SLC STT-RAM | MLC STT-RAM |
| | Read latency (cycles) | 7.43 | 9.08 | S:6.73, H:9.80 | | Read dyn. eng. (nJ) | 0.161 | 0.216 | S:0.22, H:0.43 | | Write latency (cycles) | 5.78 | 25.58 | S:25.31, H:56.50 | | Write dyn. eng. (nJ) | 0.156 | 0.839 | S:0.843, H:2.502 | | Leakage power (mW) | 295.58 | 18.39 | 7.02 | | Array area (mm2) | 7.28 | 1.86 | 1.01 |
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