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Research Article

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Table 1

Parameters of SRAM, SLC STT-RAM, and MLC STT-RAM.


Read latency (cycles)7.439.08S:6.73, H:9.80
Read dyn. eng. (nJ)0.1610.216S:0.22, H:0.43
Write latency (cycles)5.7825.58S:25.31, H:56.50
Write dyn. eng. (nJ)0.1560.839S:0.843, H:2.502
Leakage power (mW)295.5818.397.02
Array area (mm2)7.281.861.01

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