State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Table 3

Switching currents of MLC STT-RAM cell (A).

	To
From	R00	R01	R10	R11
R00	0	−38.3	—	−56.7
R01	26.3	0	—	−56.7
R10	66.4	—	0	−9.1
R11	66.4	—	39.3	0