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Research Article

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Table 5

The configurations of MLC STT-RAM.

MLC STT-RAM

Total read time (ns)S:1.25 H:1.63
Total write time (ns)S:7.18 H:14.86
Read energyS:0.018 H:0.023
Write energyS:0.087 H:0.14
Wearing/per writeHard domain: 0, 0, 1, 1 for ZT, ST, HT and TT, respectively
Soft domain: 0, 1, 1, 2 for ZT, ST, HT and TT, respectively

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