First Steps in Creating Online Testable Reversible Sequential Circuits

<div>Reversible realization of the four-bit falling-edge triggered up/down counter with asynchronous load [<a href="/journals/vlsi/2018/6153274/#B43">43</a>].</div>

VLSI Design

fig7

Figure 7

Figure 7: First Steps in Creating Online Testable Reversible Sequential Circuits 