First Steps in Creating Online Testable Reversible Sequential Circuits

<table class="table-group" id="tab3"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr class="thead"><td class="align_left">Present state</td><td class="align_center">Next state</td><td class="align_center">Modified next state</td></tr><tr class="thead"><td class="align_left"><span style="width: 62.838ptpx;"><svg height="10.7866pt" id="M117" style="vertical-align:-2.150701pt" version="1.1" viewbox="-0.0498162 -8.6359 62.838 10.7866" width="62.838pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M699 368C699 549 574 666 407 666C186 666 23 488 23 277C23 113 129 -3 288 -13L307 -26C431 -111 501 -139 533 -147C559 -154 613 -163 658 -164L666 -141C597 -111 507 -66 430 -11L416 -1C580 42 699 190 699 368ZM601 371C601 227 518 54 381 22L354 40L278 24C175 47 120 145 120 269C120 451 235 631 398 631C540 631 601 521 601 371Z" id="g113-82"></path></g><g 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451 384 474 384 503C384 579 325 635 236 635H235C182 635 136 610 108 579L65 516L85 496C110 533 150 575 205 575C258 575 300 543 300 481C300 407 232 369 141 339L147 310C163 315 188 321 211 321C268 321 338 284 338 192C338 94 288 40 217 40C160 40 119 68 93 91C85 98 77 97 69 91C60 84 47 71 46 58C44 46 48 35 62 22C75 10 116 -12 162 -12C234 -12 424 62 424 224C424 297 373 359 285 376V378Z" id="g113-52"></path></g><g transform="matrix(.0091,0,0,-0.0091,15.626,-5.741)"><path d="M486 158C486 177 478 202 466 220C413 228 386 236 336 262C386 288 413 297 466 304C478 323 486 347 485 366C470 376 444 381 422 380C389 338 368 319 321 288C323 345 329 372 349 422C339 442 322 461 305 470C289 461 271 442 262 422C281 372 287 345 290 288C243 319 222 338 189 380C167 381 142 376 125 366C125 347 133 322 145 304C198 296 225 288 275 262C225 236 198 227 145 220C133 201 125 177 126 158C141 148 167 143 189 144C222 186 243 205 290 236C288 179 282 152 262 102C272 82 289 63 306 54C322 63 340 82 350 102C330 152 324 179 321 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class="align_left">0111</td><td class="align_center"> 1000</td><td class="align_center"> 1111</td></tr><tr><td class="align_left">1000</td><td class="align_center"> 1001</td><td class="align_center"> 0001</td></tr><tr><td class="align_left">1001</td><td class="align_center"> 1010</td><td class="align_center"> 0011</td></tr><tr><td class="align_left">1010</td><td class="align_center"> 1011</td><td class="align_center"> 0001</td></tr><tr><td class="align_left">1011</td><td class="align_center"> 1100</td><td class="align_center"> 0111</td></tr><tr><td class="align_left">1100</td><td class="align_center"> 1101</td><td class="align_center"> 0001</td></tr><tr><td class="align_left">1101</td><td class="align_center"> 1110</td><td class="align_center"> 0011</td></tr><tr><td class="align_left">1110</td><td class="align_center"> 1111</td><td class="align_center"> 0001</td></tr><tr><td class="align_left">1111</td><td class="align_center"> 0000</td><td class="align_center"> 1111</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Truth table representing the next states and the modified next states of a four-bit up counter [<a href="/journals/vlsi/2018/6153274/#B43" target="_blank">43</a>].

VLSI Design

tab3

Table 3

Table 3: First Steps in Creating Online Testable Reversible Sequential Circuits 