First Steps in Creating Online Testable Reversible Sequential Circuits

Table 4

Comparison of reversible realization of the four-bit falling-edge triggered up/down counter with asynchronous load with that in [26] (including data previously presented in [43]).

	Quantum cost	Ancilla input
Design of [26]	94	8
Present design	74	8
% improvement over design of [26]	21.28	0