Novel Verification Method for Timing Optimization Based on DPSO

<div>Combinational logic circuit with <svg height="6.1673pt" id="M46" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 6.6501 6.1673" width="6.6501pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M495 86L479 114C446 82 419 66 409 66C401 66 401 72 406 97C420 166 436 231 453 297C489 435 454 448 428 448C406 448 384 439 354 422C305 394 222 327 161 247H159L183 345C200 415 194 448 173 448C143 448 82 410 23 351L38 325C64 349 95 371 105 371C111 371 116 365 109 336L25 -4L31 -12C50 -4 77 3 107 9C119 69 132 122 145 168C197 254 321 381 370 381C387 381 393 374 378 305L329 95C309 17 320 -12 345 -12C372 -12 430 19 495 86Z" id="g113-111"></path></g></svg> inputs and <svg height="6.1673pt" id="M47" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 10.3951 6.1673" width="10.3951pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M766 88L752 113C719 83 690 64 681 64C674 64 672 74 679 103L724 292C758 436 724 448 701 448C680 448 666 442 639 429C594 407 514 350 441 252H439L447 289C476 423 450 448 419 448C398 448 379 441 355 427C307 400 234 344 162 249H160L180 324C203 409 197 448 170 448C144 448 82 413 23 349L35 321C57 343 96 374 108 374C115 374 117 371 111 341C87 227 57 112 24 -6L32 -12C53 -4 81 4 108 6C119 68 134 128 149 171C177 229 309 383 364 383C387 383 388 355 373 282C354 190 330 92 303 -6L309 -12C332 -4 356 3 386 6C396 63 411 122 424 171C458 236 590 383 642 383C658 383 664 369 652 315L603 91C587 20 593 -12 619 -12C642 -12 708 23 766 88Z" id="g113-110"></path></g></svg> outputs, where the inputs are <svg height="12.689pt" id="M48" style="vertical-align:-3.40067pt" version="1.1" viewbox="-0.0498162 -9.28833 87.067 12.689" width="87.067pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g 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viewbox="-0.0498162 -8.6359 12.3847 11.927" width="12.3847pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M640 650H413L406 622L438 617C475 611 483 605 463 571C422 503 346 400 296 333C264 403 215 529 199 575C189 604 191 614 228 618L262 622L271 650H30L23 622C90 615 97 609 119 553L212 321C222 295 223 285 218 259L193 127C176 39 167 33 82 28L76 0H350L356 28C266 36 257 40 275 127L303 266C308 290 314 302 328 322C396 418 454 493 498 546C551 610 565 616 631 622L640 650Z" id="g113-90"></path></g><g transform="matrix(.0091,0,0,-0.0091,7.111,3.132)"><path d="M485 418C485 434 469 451 441 451C389 451 312 387 255 335C221 304 194 278 159 242H157L259 678C264 698 264 710 255 710C242 710 183 681 96 673L90 643L128 642C165 641 171 640 162 602L24 -5L31 -12C51 -4 81 4 110 9L145 181C154 195 180 220 205 242C233 170 263 106 291 53C318 1 335 -12 360 -12C383 -12 425 0 483 82L463 105C437 79 411 57 400 57C388 57 378 68 355 110C329 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VLSI Design

Novel Verification Method for Timing Optimization Based on DPSO

Figure 2