Novel Verification Method for Timing Optimization Based on DPSO

Table 3

Experimental results indicative of the input port (startpoint) and the output port (endpoint) of the critical path and the minimum (Min) and average (Avg) timing delays obtained for MCNC benchmark circuits using the DPSO algorithm and DC.

Circuits		Critical path		DPSO		DC
		Startpoint	Endpoint	Min/s	Avg/s	Min/s	Avg/s
alu2	10/8	h	o	42	44	46	46
alu4	14/8	i	r	43	45	47	47
b9	41/21	b0	z0	9	9	10	10
cm85a	11/3	d	l	11	12	13	13
comp	32/3	a0	g0	21	23	25	25
count	36/16	r	z0	20	22	24	24
dalu	75/16	muse12	o14	21	26	26	26
k2	45/45	d0	e2	21	23	24	24
my_adder	33/17	f0	x0	47	51	55	55
pcler8	27/17	t	r0	12	13	14	14
pcle	19/9	l	b0	9	10	11	11
pm1	16/13	c	c1	7	7	8	8
t481	16/1	v4	v16_0	20	20	21	21
terml	34/10	d0	s0	14	15	17	17
too_large	39/3	y	p0	28	29	30	30
ttt2	25/21	m	q0	12	12	14	14
vda	17/40	l	f0	15	17	17	17

total number of inputs and outputs.